1. Field of the Invention
The present invention relates to a semiconductor memory or semiconductor device having nonvolatile memory cells with multilayer memory elements formed on both side surfaces of a transistor gate electrode.
2. Description of the Related Art
Memory cells with this structure are advantageous because they can store two bits of information per cell. Many semiconductor memories employing this structure use an oxide-nitride-oxide (ONO) multilayer memory element in which a silicon nitride charge trapping layer is sandwiched between silicon oxide insulating layers. Japanese Patent Application Publication No. 2004-56095 discloses a memory of this type, in which the gate electrode is flanked on both sides by L-shaped first silicon oxide insulating layers, the silicon nitride trapping layers are seated in these insulating layers, and second silicon oxide insulating layers cover both the trapping layers and the edges of the first insulating layers. Japanese Patent Application Publication No. 2004-343015 discloses a generally similar memory in which the silicon nitride trapping layers are also L-shaped, and the second silicon oxide insulating layers are seated in the trapping layers. These memories are programmed by hot electron injection from the channel beneath the gate into the trapping layer, the electrons passing through the first insulating layer.
In these memories, the transistor gates and their multilayer memory elements are covered by an interlayer dielectric film of silicon oxide. Contact holes are formed in the interlayer dielectric film by an anisotropic etching process to provide electrical access to the source and drain areas of the substrate on both sides of the gate. A problem is that if the contact holes are misaligned, the anisotropic etching process may etch through part of the multilayer memory elements, reducing or eliminating the region in which hot electron injection takes place, thus making it difficult or impossible to program the memory cells.
To avoid this reliability problem, it is necessary to allow a margin of space between the contact holes and the multilayer memory elements, but that is undesirable because it makes the memories larger and more expensive.
As an alternative structure, Japanese Patent Application Publication No. 2004-343015 also discloses a memory in which the multilayer memory element has an inverted U-shape that covers the top and sides of the gate electrode. The U-shaped memory element is covered by a further outer layer of silicon nitride seventy to two hundred nanometers thick. The anisotropic etching process that forms the contact holes is highly selective, etching silicon nitride much more slowly than silicon oxide, so even if the contact holes are misaligned, the etching process does not penetrate through the thick outer silicon nitride layer and the memory elements remain undamaged.
Although this structure eliminates the need for an alignment margin, it has other disadvantages, one being that the thick outer silicon nitride layer covering the multilayer memory element, which is itself comparatively thick, limits the possible reduction in memory cell size.